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Why do I see an impact on the cycle time when I update my M580 CPU to SV2.50 ?

Published date: 15 June 2020

Enhancements have been made in SV2.50 to enhance the reliability of the access to the internal memory (activation of the ECC : Error Correcting Code activation).

In most cases, very limited impact has been measured on the cycle time of typical applications.
The biggest impact is on some redundant M580 CPU systems (hot standby) where the cycle time may increase if your application has a very small code to execute but a big set of data to manage. (ECC feature only impacts hot standby memory transfer activity, and has very little impact on user code execution performance).

Possible workarounds are to :
- reduce the amount of exchanged data from primary to standby CPU
- disable the ECC feature using system word %SW150.
   ->To disable ECC: write the value 16#DECC to %SW150 (and power cycle the CPU (note: this value has to be written again after a cold start using the reset button).
   ->To re-enable ECC after a disable: write any value different of 16#DECC  to %SW150, perform a power cycle or push reset button.

- The status of ECC is given in %S109 : 0 = ECC activated, 1 = ECC deactivated.

Note: %SW150 is transferred from primary to stand-by PAC but the Standby PAC must also be power cycled to disable ECC. Verify that %S109 is set the same in both the Primary and Standby.

Basics :
- ECC (Error Correcting Code) corrects modern memories random access errors, but can slow down the memory access time.
- ECC feature only impacts  hot standby memory transfer activity, and has very little  impact on user code execution performance.
- ECC disable feature (%SW150, %S109) is only supported in M580 Hot Standby systems.
- Memory management optimizations have been deployed to compensate memory access time degradation.

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