Due to a limitation of the internal ADC (analog to digital converter) electronic component, if the slew rate (dV/dt) between 2 acquisitions of a given channel overtakes the max input slew rate characteristic, (the value is stated in the FW history and in the table below), then the module micro controller software needs to execute a heavy post treatment of the sample values of that channel.
This will impact that channel acquisition time and the global acquisition cycle time.
During this post treatment, the previous correctly sampled value of the given channel will still be available for the CPU module.
If the CPU module task cycle time is smaller than the AMI global acquisition cycle time, then the CPU may read duplicate input values.
The AMI global acquisition cycle time is the sum of the channels acquisition time. (plus a management fixed time)
The global acquisition cycle time of the AMI depends on the configuration of the module (2 acquisition modes are available).
In normal mode, all input channels are scanned.
In fast mode, only the activated channels are scanned, which leads to a smaller cycle acquisition cycle time.
NOTE: we don't discuss here the digital filtering feature that computes a given input samples to return an average value, but only raw input values.
In case the slew rate (dV/dt or dA/dt) of the analog signal to digitize is lower than ("400mV/T" or "1.6mA/T" with T equal to "1ms+1ms*nber of channels used"), then the acquisition cycle time is equal to T. So, for example :
- with only one input configured, the acquisition cycle time is 2 ms
- with 8 inputs configured, the acquisition cycle time is 9 ms
In case the slew rate (dV/dt or dA/dt) of the analog signal to digitize is higher than (("400mV/T" or "1.6mA/T" with T equal to "1ms+1ms*nber of channels used"), then the acquisition cycle time is equal to "16+T*2 ms". So, for example :
- with only one input configured, the acquisition cycle time is 20 ms
- with 8 inputs configured, the acquisition cycle time is 34 ms
發佈於: 施耐德電機Taiwan
